Automated computerized system integrity test of Signalling and Systems for Railways
System integrity test [SIT] is conducted to ensure compliance of functional and safety requirements of signaling system by simulating various states of signaling elements before bringing signaling system into service. This is part of System Acceptance Test [SAT]. SIT is the most important activity of the signaling system commissioning. Present process of system integrity test is based on certification by the testing personnel after conducting the test. Evidence of testing by tester is not provided for verification. Human errors of tester are common.
A new PC based system integrity test using data logger system, which creates evidence of testing and eliminates human errors is developed and tested on Indian Railways.
A. Present process of signaling system design, wiring and testing on Indian Railways
I. Design
i. Design of SIP [Signalling and Interlocking Plan] based on Track Plan
ii. Design of Table of Control [TOC] based on SIP
iii. Design of circuits based on SIP and TOC
II. Wiring and testing
i. Wiring of relays as per circuit wiring diagrams
ii. Testing of physical wiring by continuity test
iii. Wiring of test set up with dummy loads to simulate signalling elements
iv. Conducting tests as per TOC by simulated signalling elements
III. Limitations of present practice of testing
i. Test procedure is not unique for the tests; except for the most common type of tests like negative test
ii. No evidence is shown for conductance of test. No scope for verification of tests conducted as no evidence is produced after completion of testing.
iii. Testing; completely depends on the skill of the person testing. Human errors cannot be ruled out.
B. New practice of Automated Computerised System Integrity Test
By conducting system integrity test on signaling system, errors in circuit design and circuit wiring are detected. Signaling systems are amenable for automated computerized testing as the sequence of activities is precise and repetitive; results are predictable.
I. 3 Stages of development of automated computerized system integrity testing: [FIG.2]
Stage 1: Defining the tests in minute activities in sequence
Stage 2: Development of software which enables
i. Driving a specially made processor based hardware for operations on operating panel and changing states of signaling elements
ii. Creating TEST PLAN with expected results
iii. Obtaining response of the signaling system i.e. test results in the form of relays’ status from data logger
iv. Comparing test results obtained from data logger with expected test results and declaring the success or failure of the test
Stage 3: Development of hardware which can be controlled by the software developed at 2 above for controlling the operating panel and the state of signaling elements
II. Defining the Tests:
System integrity test consists of the following tests to ensure compliance of the signaling system to various safety conditions mentioned in the manuals and codes and rules and regulations issued by railway administration.
1. Positive test: Signal is cleared from PC through test software. The software checks that the Signal is cleared only after corresponding route is checked (UCR up), locked ( ASR down ) and other conditions of TOC are satisfied
2. Negative Test - by controlling each signal element, i. e. dropping track circuits, dropping points detection relays, crank handle, L.C. Gate Controls one at a time; it is positively ensured that each element is controlling the signal
3. Route Release Test for light engine and long train – by dropping and picking up track circuits sequentially through software, train movement is simulated. At each stage of occupation and clearance of each track circuit, picking up of required route release relays as per the design are checked.
4. Route holding Test - sequential train movement is simulated – before normalizing signal control the back locking track under test is dropped. Route is released only after picking up of back locking track.
5. One Signal – One Train Test – after dropping first controlling track circuit the signal goes back to danger, even after picking up of track circuit signal does not come back to yellow/green since TSR drops.
6. Approach Locking Test - when approach track is down signal is cleared. Then Signal is put back to danger - Route Cancellation timer is ON. DROP the controlling track, Timer shall stop. Pick up the track, Timer shall start.
7. Route locking test – after clearing the signal, attempt is made to operate the points or transmit gate control, crank handle control
8. SM lock effectiveness test – after locking the panel by dropping panel locking relay, attempt is made to operate the point, signal and gate control
9. Point track locking test – point controlling track circuit is dropped one at a time and attempted to operate the point
10. Checking of incorporation of other than the conditions given in TOC/RCC – after clearing the signal all the unrelated tracks and points are dropped and checked whether the signal changed its aspect
11. Signal aspect sequencing test: observing the dependency of the signal aspect on the signal ahead by changing the aspect of signal ahead
12. Square sheet test: after clearing a signal to a route, all other routes are tried to check for their permissibility
III. Development of hardware:
i. Controlling the button/switch of the panel:
A miniature relay is used to control the button/switch by looping the button/switch contact with its potential free contact at panel termination rack as shown below
ii. Controlling the state of signaling elements [point, signal, track circuit, LC Gate, Crank handle etc.]:
State of the signaling element is simulated by disconnecting the signaling element at out-door cable termination rack and connecting to dummy element. A miniature relay is used to control the status of the signaling element as shown below.
Note:
IV. Process of testing:
i. Generation of test plan:
1. Identification of inputs to data logger keeping in view the TOC and test procedure and wiring the inputs and validation of data logger inputs data base
2. Identification of signaling elements whose states are to be changed to carry out the tests as per TOC and nomination of miniature relay for each element state
3. Identification of buttons and switches which are required to be operated to carry out the tests based on panel diagram nomination of miniature relay for each switch/button
4. Entering in the software the details of data logger inputs and miniature relays controlling panel and signaling elements
5. Generation of test plan and manual verification of one test case of each test for its correctness
6. Getting approval for test plan from customer
ii. Conducting the test:
1. Getting details of panel and cable termination rack for incorporating the potential free contact of the miniature relays for panel operation and changing the state of signaling element through software
2. Wiring the potential free contacts of the miniature relays
3. Conducting the test by actuation from PC loaded with test plan software of the station
Giving test results to Railways with evidence of status of relays and reconciling the anomalies if any.
V. Test results
Format of test result is given below:
Test name
|
Operation
|
Expected result
|
Actual result
|
Success
|
1A-A route Point negative test attempted
|
52 Point indication drop initiated:
52 NWKR Down
01/04/2011 09:28:51:0
|
52 NWKR Down
1A UCR Down
1A HR Down
|
52 NWKR Down
01/04/2011 09:28:51:312
1A UCR Up
01/04/2011 09:28:50:766
1A HR Down
01/04/2011 09:28:51:344
|
No
|
Explanation to the table contents:
Test name: Name of the test
Operation: Command given by test software to the test system
Expected result: Response of the signaling system in terms of relays status change as per test plan
Actual result: Response of the signaling system in terms of relays status change obtained from data logger
Success: Test is evaluated by comparing expected results and actual results. If there is no deviation result is declared as ‘yes’. If there is deviation, result is declared as ‘no’.
Tests are conducted at several stations on Indian Railways and Typical deviations are due to:
1. Omissions in circuit design: not implementing required condition
2. Commissions in circuit design: implementing additional [wrong] conditions
3. Wrong wiring: resulting omission or commission of conditions or not meeting functional requirements
4. TOC corrections: certain conditions required to be provided in TOC but missed, still provided in the circuit design
Time taken to conduct the test:
For station with about 50 routes:
It takes hardly 20 minutes to conduct all tests for one route after bypassing 2 minutes time delay for cancellation of route.
For stations with about 700 routes:
It takes about 45 minutes per route to conduct all tests except square sheet test. Square sheet test takes about 3 hours per route.
i. Suitability for testing Electronic Interlocking:
It is possible to implement computerized system integrity test on Electronic Interlocking as it is if physical operating panel is provided apart from VDU operation.
In case object controllers are used testing system also gets distributed as the access for signaling elements states is available at the object controller.
Summing up:
i. Signaling system availability improves
ii. More accurate testing in less time
iii. Testing made independent of human errors due to fatigue
iv. Testing to a large extent made independent of testing capability of the tester
v. Document of Test Plan is generated automatically, which can be verified for completeness and correctness before commencement of testing
vi. Evidence of Testing and Test results made available for future reference
